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HT45R0072I/O 8-Bit MCU with USB InterfaceFeatures· Operating voltage:· Fully integrated 6MHz or 12MHz oscillatorfSYS 6M/12MHz: 3.6V 5.5V (VBUS)· All I/O pins have wake-up functions· Low voltage reset function· Power-down function and wake-up feature reduce· 34 bidirectional I/O lines (max.)power consumption· 8-bit programmable timer/event counter with· 8-level subroutine nestingoverflow interrupt· Up to 0.33ms instruction cycle with 12MHz system· 16-bit programmable timer/event counter withclock at VDD 3.3Voverflow interrupt· Bit manipulation instruction· Watchdog Timer· 16-bit table read instruction· PS2 and USB modes supported· 63 powerful instructions· USB 2.0 low speed function· All instructions in one or two machine cycles· 3 endpoints supported - endpoint 0 included· Dice, 46-QFN packages· 4096 16 program memory· 160 8 data memory RAM· Integrated 1.5kW resistor between V33O andUSBPDN pins for USB applicationsGeneral DescriptionThe HT45R0072 is 8-bit high performance, RISC architecture microcontroller devices specifically designed formultiple I/O control product applications.and wake-up functions, Watchdog timer etc, make thedevices extremely suitable for use in computer peripheralproduct applications as well as many other applicationssuch as industrial control, consumer products, subsystem controllers, etc.The advantages of low power consumption, I/O flexibility,timer functions, integrated USB interface, Power DownRev. 1.001December 21, 2016

HT45R0072Block DiagramW a tc h d o gT im e rW a tc h d o gT im e r O s c illa to rR e s e tC ir c u it8 - b itR IS CM C UC o reP ro g ra mM e m o ryD a taM e m o ryS ta c kIn te rru p tC o n tr o lle rL o wV o lta g eR e s e tIn te rn a lR C O s c illa to rU S BI/OP o rts8 - b itT im e r1 6 - b itT im e rV 3 3 OPin /TMR1NCNCPB0PB1PB2PB3PB4PB5PB6PB7VBUS12345678946 45 44 43 42 41 40 39 38 37 36 35 34 33HT45R007246 QFN-A10 11 1213 14 15 16 17 18 19 20 21 22 PC2PC1PC0RESVPPVSSPE1PE0USBPDPUSBPDNVDD/ V33ONCNCRev. 1.002December 21, 2016

HT45R0072Pin DescriptionPin NameI/OOptionsDescriptionBidirectional 8-bit input/output port. Each pin can be configured as aPull-highwake-up input by a configuration option. Software instructions deterWake-upmine if the pin is a CMOS output or Schmitt Trigger input. ConfiguraNMOS/CMOS/PMOS tion options determine if the pins have pull-high resistors. TMR0 andTMR1 are pin-shared with PA6 and PA7, respectively.PA0 PA5PA6/TMR0PA7/TMR1I/OPB0 PB7I/OPull-highWake-upBidirectional 8-bit input/output port. Each nibble can be configured asa wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors.I/OPull-highWake-upBidirectional 8-bit input/output port. Each nibble can be configured asa wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors.PD0 PD7I/OPull-highWake-upBi-directional 8-bit input/output port. Each nibble can be configuredas a wake-up input by a configuration option. Software instructionsdetermine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors.PE0 PE1I/OPull-highWake-upBidirectional 2-bit input/output port. Each pin can be configured as awake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors.USBPDP/CLKI/O¾USBPDP line. USB function is controlled by software control registerUSBPDN/DATAI/O¾USBPDN line. USB function is controlled by software control registerRESI¾Schmitt trigger reset input. Active lowVSS¾¾Digital negative power supply, groundVDD¾¾Digital positive power supply (V33O)V33OO¾3.3V regulator outputVBUS¾¾USB bus power supplyVPP¾¾OTP programming voltage power supplyPC0 PC7Absolute Maximum RatingsSupply Voltage (VBUS).VSS-0.3V to VSS 6.0VStorage Temperature .-50 C to 125 CSupply Voltage (VDD).VSS-0.3V to VDD 3.6VOperating Temperature.-40 C to 85 CIOL Total .150mAIOH Total.-100mAInput Voltage.VSS-0.3V to VDD 0.3VTotal Power Dissipation .500mWNote: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² maycause substantial damage to the device. Functional operation of this device at other conditions beyond those listedin the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.Rev. 1.003December 21, 2016

HT45R0072D.C. CharacteristicsTa 25 CTest tionsVBUSOperating Voltage¾USB Bus power input(VBUS pin)3.6¾5.5VVDDOperating Voltage¾MCU internal power, Voltagefrom internal 3.3V Regulator3.03.33.6VIDD1¾12mA5VNo load, fSYS 6MHz6.5Operating CurrentNo load, fSYS 12MHz¾7.516mA¾¾400mAISUSSuspend Current(fSYS off, fWDT on)5VNo load, USB suspend,set CLK adj 3.3V Regulator on,ESDC 0 (SCC.0),CLK adj 1(SCC.7),MODE CTRL[10] 10BISTBStandby Current(fSYS off, fWDT on)5VNo load, set CLK adj 3.3VRegulator on, SCC 80hMODE CTRL[10] 11B¾¾150mAVIL1Input Low Voltage(I/O, TMR0/1)5VI/O power VDD0¾0.2VDDVVIH1Input High Voltage(I/O, TMR0/1)5VI/O power VDD0.8VDD¾VDDVVIL2Input Low Voltage (RES)5VI/O power VDD0¾0.4VDDVVIH2Input High Voltage (RES)5VI/O power VDD0.9VDD¾VDDVIOLI/O Port Sink Current5VVOL 0.1VDD24¾mAIOHI/O Port Source Current5VVOH 0.9VDD-2-4¾mAVLVRLow Voltage Reset¾-10%2.5 10%VVV33O3.3V Regulator Output¾IV33O 70mA3.03.33.6VPull-high Resistance for I/O5VI/O power VDD VV33O2060100kWPull-high Resistance for CLK,DATA5VVBUS 5VMODE CTRL[10] 01B3.44.76.0kWPull-high Resistance forUSBPDN pin with V33O5V-5%1.5 5%kWRPHR1.5KRev. 1.00¾¾4December 21, 2016

HT45R0072A.C. CharacteristicsTa 25 CTest Hz1/fRCSYSVDDConditions3.3VfRCSYSRC Clock with 8-bit Prescaler RegistertWDTWatchdog Time-out Period(System Clock)¾¾1024¾¾tUSBUSBPDP, USBPDN Rising & Falling Time¾¾75¾300nsOscillation Start-up Timer Period¾¾¾1024¾tSYS¾¾¾5¾mstOSTtOSCsetup Crystal SetupfINO125VInternal Oscillator Frequency for 12MHz3.3V¾10.8012.0013.20MHzfINOUSBInternal Oscillator Frequency with USB Mode3.3V¾11.8212.0012.18MHzNote:tSYS 1/fSYSPower on period tWDT tOST tOSCsetupWDT Time out in Normal Mode 1/ fRCSYS 256 WDTS tWDTWDT Time out in Power Down Mode 1/ fRCSYS 256 WDTS tOST tOSCsetupPower-on Reset CharacteristicsTa 25 CTest UnitVPORVDD Start Voltage to EnsurePower-on Reset¾¾¾¾100mVRRVDDVDD raising rate to EnsurePower-on Reset¾¾0.035¾¾V/mstPORMinimum Time for VDD Stays atVPOR to Ensure Power-on Reset¾¾1¾¾msVD DtPO RR RV D DVP O RT im eRev. 1.005December 21, 2016

HT45R0072System ArchitectureA key factor in the high-performance features of theHoltek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISCmicrocontrollers providing increased speed of operationand enhanced performance. The pipelining scheme isimplemented in such a way that instruction fetching andinstruction execution are overlapped, hence instructionsare effectively executed in one cycle, with the exceptionof branch or call instructions. An 8-bit wide ALU is usedin practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation,increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through theAccumulator and the ALU. Certain internal registers areimplemented in the Data Memory and can be directly orindirectly addressed. The simple addressing methods ofthese registers along with additional architectural features ensure that a minimum of external components isrequired to provide a functional I/O and A/D control system with maximum reliability and flexibility.functions. In this way, one T1 T4 clock cycle forms oneinstruction cycle. Although the fetching and execution ofinstructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in oneinstruction cycle. The exception to this are instructionswhere the contents of the Program Counter arechanged, such as subroutine calls or jumps, in whichcase the instruction will take one more instruction cycleto execute.For instructions involving branches, such as jump or callinstructions, two machine cycles are required to complete instruction execution. An extra cycle is required asthe program takes one cycle to first obtain the actualjump or call address and then another cycle to actuallyexecute the branch. The requirement for this extra cycleshould be taken into account by programmers in timingsensitive applications.Program CounterDuring program execution, the Program Counter is usedto keep track of the address of the next instruction to beexecuted. It is automatically incremented by one eachtime an instruction is executed except for instructions,such as ²JMP² or ²CALL² that demand a jump to anon-consecutive Program Memory address. It must benoted that only the lower 8 bits, known as the ProgramCounter Low Register, are directly addressable by user.Clocking and PipeliningThe system clock is derived from an internal oscillatorand is subdivided into four internally generatednon-overlapping clocks, T1 T4. The Program Counteris incremented at the beginning of the T1 clock duringwhich time a new instruction is fetched. The remainingT2 T4 clocks carry out the decoding and executionO s c illa to r C lo c k( S y s te m C lo c k )P h a s e C lo c k T 1P h a s e C lo c k T 2P h a s e C lo c k T 3P h a s e C lo c k T 4P ro g ra mC o u n te rP ip e lin in gP CP C 1F e tc h In s t. (P C )E x e c u te In s t. (P C -1 )P C 2F e tc h In s t. (P C 1 )E x e c u te In s t. (P C )F e tc h In s t. (P C 2 )E x e c u te In s t. (P C 1 )System Clocking and PipeliningM O V A ,[1 2 H ]2C A L L D E L A Y3C P L [1 2 H ]4:5:61D E L A Y :F e tc h In s t. 1E x e c u te In s t. 1F e tc h In s t. 2E x e c u te In s t. 2F e tc h In s t. 3F lu s h P ip e lin eF e tc h In s t. 6E x e c u te In s t. 6F e tc h In s t. 7N O PInstruction FetchingRev. 1.006December 21, 2016

HT45R0072When executing instructions requiring jumps tonon-consecutive addresses such as a jump instruction,a subroutine call, interrupt or reset, etc., themicrocontroller manages program control by loading therequired address into the Program Counter. For conditional skip instructions, once the condition has beenmet, the next instruction, which has already beenfetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.If the stack is full and an enabled interrupt takes place,the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the StackPointer is decremented, by RET or RETI, the interruptwill be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stackoverflow. Precautions should be taken to avoid suchcases which might cause unpredictable programbranching.The lower byte of the Program Counter, known as theProgram Counter Low register or PCL, is available forprogram control and is a readable and writeable register.By transferring data directly into this register, a short program jump can be executed directly, however, as onlythis low byte is available for manipulation, the jumps arelimited to the present page of memory, that is 256 locations. When such program jumps are executed it shouldalso be noted that a dummy cycle will be inserted.P ro g ra mS ta c k L e v e l 1T o p o f S ta c kS ta c k L e v e l 2S ta c kP o in te rB o tto mThe lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL mightcause program branching, so an extra cycle is neededto pre-fetch. Further information on the PCL register canbe found in the Special Function Register section.P ro g ra mM e m o ryS ta c k L e v e l 3o f S ta c kS ta c k L e v e l 8Arithmetic and Logic Unit - ALUThe arithmetic-logic unit or ALU is a critical area of themicrocontroller that carries out arithmetic and logic operations of the instruction set. Connected to the mainmicrocontroller data bus, the ALU receives related instruction codes and performs the required arithmetic orlogical operations after which the result will be placed inthe specified register. As these ALU calculation or operations may result in carry, borrow or other statuschanges, the status register will be correspondingly updated to reflect these changes. The ALU supports thefollowing functions:StackThis is a special part of the memory which is used tosave the contents of the Program Counter only. Thestack has 8 levels and is neither part of the data nor partof the program space, and is neither readable norwriteable. The activated level is indexed by the StackPointer, SP, and is neither readable nor writeable. At asubroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack.At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the ProgramCounter is restored to its previous value from the stack.After a device reset, the Stack Pointer will point to thetop of the stack.ModeC o u n te r· Arithmetic operations: ADD, ADDM, ADC, ADCM,SUB, SUBM, SBC, SBCM, DAA· Logic operations: AND, OR, XOR, ANDM, ORM,XORM, CPL, CPLAProgram Counter Bitsb11b10b9b8b7b6b5b4b3b2b1b0Initial Reset000000000000USB Interrupt000000000100Timer/Event Counter 0 Overflow000000001000Timer/Event Counter 1 [email protected]@[email protected]@0SkipProgram Counter 2Loading PCLPC11 PC10 [email protected]@[email protected]@4Jump, Call Branch#11#10#9#8#7#6#5#4#3#2#1#0Return from SubroutineS11S10S9S8S7S6S5S4S3S2S1S0Program CounterNote:PC11 PC8: Current Program Counter bits#11 #0: Instruction code address bitsRev. [email protected] @0: PCL bitsS11 S0: Stack register bits7December 21, 2016

HT45R00720 0 0 H· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,RLC0 0 4 H· Increment and Decrement INCA, INC, DECA, DEC· Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,0 0 8 HSIZA, SDZA, CALL, RET, RETI0 0 C HProgram MemoryThe Program Memory is the location where the user codeor program is stored. The HT45R0072 is a One-TimeProgrammable, OTP, memory type device where userscan program their application code into the device. By using the appropriate programming tools, OTP devices offer users the flexibility to freely develop their applicationswhich may be useful during debug or for products requiring frequent upgrades or program changes. OTP devicesare also applicable for use in applications that require lowor medium volume production runs.In itia lis a tio nV e c to rU S BIn te rru p t V e c to rT im e r /E v e n t 0 C o u n te rIn te rru p t V e c to rT im e r /E v e n t 1 C o u n te rIn te rru p t V e c to rF F F H1 6 b itsProgram Memory StructureThis area is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt resultsfrom a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the programjumps to this location and begins execution.· Table locationStructureAny location in the program memory can be used aslook-up tables. There are three methods to read theProgram Memory data using two table read instructions: ²TABRDC² and ²TABRDL², transfer the contents of the lower-order byte to the specified datamemory, and the higher-order byte to TBLH (08H).The three methods are shown as follows:The Program Memory has a capacity of 4K by 16 bits.The Program Memory is addressed by the ProgramCounter and also contains data, table information andinterrupt entries. Table data, which can be setup in anylocation within the Program Memory, is addressed byseparate table pointer registers. Using the instruction ²TABRDC [m]² for the currentProgram Memory page, where one page 256words, where the table location is defined byTBLP in the current page. This is where the configuration option has disabled the TBHP register. Using the instruction ²TABRDC [m]², where the table location is defined by registers TBLP and TBHP.Here the configuration option has enabled theTBHP register. Using the instruction ²TABRDL [m]², where the table location is defined by registers TBLP in the lastpage which has the address range 0F00H 0FFFH.Special VectorsWithin the Program Memory, certain locations are reserved for special usage such as reset and interrupts.· Location 000HThis area is reserved for program initialization. Afterchip reset, the program always begins execution at location 000H.· Location 004HThis area is reserved for the USB interrupt serviceprogram. If the USB interrupt is activated, the interruptis enabled and the stack is not full, the program jumpsto this location and begins execution.Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word aretransferred to the lower portion of TBLH, and the remaining 1-bit words are read as ²0². The TableHigher-order byte register (TBLH) is read only. The table pointers, TBLP and TBHP, are read/write registers, which indicate the table location. Beforeaccessing the the table, the locations must be placedin the TBLP and TBHP registers (if the configuration· Location 008HThis area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt resultsfrom a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the programjumps to this location and begins execution.· Location 00CHTable Location BitsInstructionb11b10b9b8b7b6b5b4b3b2b1b0TABRDC [m][email protected]@[email protected]@[email protected]@[email protected]@0TABRDL [m][email protected]@[email protected]@[email protected]@[email protected]@0Table LocationNote:PC11 PC8: Current Program Counter bitsTBHP register Bit 3 Bit 0 when TBHP is [email protected] @0: Table Pointer TBLP bitsRev. 1.008December 21, 2016

HT45R0072option has disabled TBHP then the value in TBHP hasno effect). TBLH is read only and cannot be restored.If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to bechanged by the table read instruction used in the ISRand errors can occur. Using the table read instructionin the main routine and the ISR simultaneously shouldbe avoided. However, if the table read instruction hasto be applied in both the main routine and the ISR, theinterrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH hasbeen backed up. All table related instructions requiretwo cycles to complete the operation. These areasmay function as normal program memory dependingon the requirements.Once TBHP is enabled, the instruction ²TABRDC [m]²reads the Program Memory data as defined by theTBLP and TBHP values. If the Program Memory codeoption has disabled TBHP, the instruction ²TABRDC[m]² reads the Program Memory data as defined byTBLP only in the current Program Memory page.retrieved from the current Program Memory page or lastProgram Memory page using the ²TABRDC[m]² or²TABRDL [m]² instructions, respectively. When theseinstructions are executed, the lower order table bytefrom the Program Memory will be transferred to the userdefined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH specialregister. Any unused bits in this transferred higher orderbyte will be read as ²0².Table Program ExampleThe following example shows how the table pointer andtable data is defined and retrieved from themicrocontroller. This example uses raw table data located in the last page which is stored there using theORG statement. The value at this ORG statement is²F00H² which refers to the start address of the last pagewithin the 4K Program Memory of device. The tablepointer is setup here to have an initial value of ²06H².This will ensure that the first data read from the data table will be at the Program Memory address ²F06H² or 6locations after the start of the last page. Note that thevalue for the table pointer is referenced to the first address of the present page if the ²TABRDC [m]² instruction is being used. The high byte of the table data whichin this case is equal to zero will be transferred to theTBLH register automatically when the ²TABRDL [m]² instruction is executed.Look-up TableAny location within the Program Memory can be definedas a look-up table where programmers can store fixeddata. To use the look-up table, the table pointer mustfirst be setup by placing the lower order address of thelook up data to be retrieved in the TBLP register and thehigher order address in the TBHP register. These tworegisters define the full address of the look-up table.Using the TBHP must be selected by configuration option, if not used table data can still be accessed but onlythe lower byte address in the current page or last pagecan be defined.After setting up the table pointers, the table data can beP ro g ra m C o u n te rH ig h B y teT B H PP ro g ra mM e m o ryT B L PT B L HT a b le C o n te n ts H ig h B y teT B L HS p e c ifie d b y [m ]T a b le C o n te n ts L o wH ig h B y te o f T a b le C o n te n tsB y teS p e c ifie d b y [m ]L o w B y te o f T a b le C o n te n tsTable Read - TBLP/TBHPTable Read - TBLP onlyRev. 1.00P ro g ra mM e m o ryT B L P9December 21, 2016

HT45R0072tempreg1 dbtempreg2 db::?; temporary register #1; temporary register #2mov a,06h; initialise table pointer - note that this address is referencedmov tblp,a::; to the last page or present pagetabrdl; transfers value in table referenced by table pointer to tempregl; data at prog. memory address ²F06H² transferred to tempreg1 and TBLHtempreg1dec tblptabrdl; reduce value of table pointer by onetempreg2::org F00hdc;;;;;transfers value in table referenced by table pointer to tempreg2data at prog.memory address ²F05H² transferred to tempreg2 and TBLHin this example the data ²1AH² is transferred totempreg1 and data ²0FH² to register tempreg2the value ²00H² will be transferred to the high byte register TBLH; sets initial address of last page00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh::Because the TBLH register is a read-only register andcannot be restored, care should be taken to ensure itsprotection if both the main routine and Interrupt ServiceRoutine use the table read instructions. If using the tableread instructions, the Interrupt Service Routines maychange the value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table readinstructions should be avoided. However, in situationswhere simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of anymain routine table-read instructions. Note that all tablerelated instructions require two instruction cycles tocomplete their operation.mon to all microcontrollers, such as ACC, PCL, etc.,have the same Data Memory address.General Purpose Data MemoryAll microcontroller programs require an area ofread/write memory where temporary data can be storedand retrieved for use later. It is this area of RAM memorythat is known as General Purpose Data Memory. Thisarea of Data Memory is fully accessible by the user program for both read and write operations. By using the²SET [m].i² and ²CLR [m].i² instructions, individual bitscan be set or reset under program control giving theuser a large range of flexibility for bit manipulation in theData Memory.Data Memory0 0 HS p e cP u rp oD aM e m oThe Data Memory is a volatile area of 8-bit wide RAMinternal memory and is the location where temporary information is stored. Divided into two sections, the first ofthese is an area of RAM where special function registersare located. These registers have fixed locations andare necessary for correct operation of the device. Manyof these registers can be read from and written to directly under program control, however, some remainprotected from user manipulation. The second area ofData Memory is reserved for general purpose use. Alllocations within this area are read and write accessibleunder program control.3 F H4 0 HG e n e ra lP u rp o s eD a taM e m o ryD F HData Memory StructureNote:StructureThe two sections of Data Memory, the Special Purposeand General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are8 bits wide. The start address of the Data Memory for alldevices is the address ²00H². Registers which are comRev. 1.00ia ls etary10Most of the Data Memory bits can be directlymanipulated using the ²SET [m].i² and ²CLR[m].i² with the exception of a few dedicated bits.The Data Memory can also be accessedthrough the memory pointer register MP.December 21, 2016

HT45R0072Special Purpose Data MemorySpecial Function RegistersThis area of Data Memory is where registers, necessaryfor the correct operation of the microcontroller, arestored. It is divided into two banks, Bank 0 and Bank1.Most of the registers are both readable and writeablebut some are protected and are readable only, the details of which are located under the relevant SpecialFunction Register section. Note that for locations thatare unused, any read instruction to these addresses willreturn the value ²00H².To ensure successful operation of the microcontroller,certain internal registers are implemented in the DataMemory area. These registers ensure correct operationof internal functions such as timers, interrupts, etc., aswell as external functions such as I/O data control. Thelocation of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and thepoint where the General Purpose Memory begins is reserved and attempting to read data from these locationswill return a value of 00H.The Special Purpose Registers for the USB interfaceare stored in Bank 1 which can only be accessed by firstsetting the Bank Pointer to a value of 01H and then using Indirect Addressing Register IAR1 and MemoryPointer MP1. Bank 1 can only be accessed indirectly using the MP1 Memory Pointer, direct addressing is notpossible.0 0 H0 1 H0 2 H0 3 H0 4 H0 5 H0 6 H0 7 H0 8 H0 9 H0 A H0 B H0 C H0 D H0 E H0 F H1 0 H1 1 H1 2 H1 3 H1 4 H1 5 H1 6 H1 7 H1 8 H1 9 H1 A H1 B H1 C H1 D H1 E H1 F H2 0 H2 1 H2 2 H2 3 HB aIAMIAMn k 0R 0P 0R 1P 1B PA C CP C LT B L PT B L HW D T SS T A T U SIN T C4 0 H4 1 H4 2 H4 3 H4 4 H4 5 H4 6 H4 7 H4 8 H4 9 H4 A HIndirect Addressing Register - IAR0, IAR1The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM registerspace, do not actually physically exist as normal registers. The method of indirect addressing for RAM datamanipulation uses these Indirect Addressing Registersand Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result inno actual read or write operation to these registers butrather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as apair, IAR0 and MP0 can together only access data fromBank 0, while the IAR1 and MP1 register pair can access data from both Bank 0 and Bank 1. As the IndirectAddressing Registers are not physically implemented,reading the Indirect Addressing Registers indirectly willreturn a result of ²00H² and writing to the registers indirectly will result in no operation.B a n k 1U S B S T A TP IP E C T R LA W RS T A L LP IP ES IE SM IS CE N D P T E NF IF O 0F IF O 1F IF O 2T M R 0T M R 0 CT M R 1 HT M R 1 LT M R 1 CP AP A CP BP B CP CP C CP DP D CP EP E CT BUUSH PS CS RC CMemory Pointer - MP0, MP1For all devices, two Memory Pointers, known as MP0and MP1 are provided. These Memory Pointers arephysically implemented in the Data Memory and can bemanipulated in the same way as normal registers providing a convenient way with which to address and trackdata. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address thatthe microcontroller is directed to, is the address specified by the related Memory Pointer. MP0 can only access data in Bank 0 while MP1 can access both banks.: U n u s e d re a d a s "0 "Special Purpose Data MemoryRev. 1.0011December 21, 2016

HT45R0072data .section data adres1db ?adres2db ?adres3db ?adres4db ?blockdb ?code .section at 0 code org 00hstart:movmovmovmova,04hblock,aa,offset adres1mp0,a; setup size of blockloop:clrincsdzjmpIAR0mp0blockloop; clear the data at address defined by MP0; increment memory pointer; check if last memory location has been cleared; Accumulator loaded with first RAM address; setup memory pointer with first RAM addresscontinue:The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses.Accumulator - ACCdata pointing and reading. TBLH is the location where thehigh order byte of the table data is stored after a table readdata instruction has been executed.The Accumulator is central to the operation of anymicrocontroller and is closely related with operationscarried out by the ALU. The Accumulator is the placewhere all intermediate results

PS2 and USB modes supported USB 2.0 low speed function 3 endpoints supported - endpoint 0 included 409616 program memory 1608 data memory RAM Integrated 1.5k resistor between V33O and USBPDN pins for USB applications Fully integrated 6MHz or 12MHz oscillator All I/O pins have wake-up fun