Transcription

1OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

ContentsChapter 1 OpenVINO Starter Kit . 41.1Package Contents. 41.2OpenVINO Starter Kit System CD . 51.3Getting Help . 5Chapter 2 Introduction of the OpenVINO Starter Kit. 62.1Layout and Components . 62.2Block Diagram of the OpenVINO Starter Kit . 7Chapter 3 Using the OpenVINO Starter Kit . 103.1Configuring the Cyclone V FPGA . 103.2Board Status Elements . 143.3Clock Circuitry . 153.4Peripherals Connected to the FPGA . 16Chapter 4OpenVINO Starter Kit System Builder . 354.1Introduction . 354.2General Design Flow. 354.3Using OpenVINO Starter Kit System Builder . 36Chapter 5Examples of Advanced Demonstrations . 415.1OpenVINO Starter Kit Factory Default Configuration . 415.2Nios II SDRAM Test . 425.3Verilog SDRAM Test. 455.4DDR3 SDRAM Test . 465.5DDR3 SDRAM Test by Nios II . 485.6UART Control. 515.7ADC Reading . 56Chapter 6 Programming the EPCQ . 612OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

6.1Convert .sof File to .jic File . 616.2Write.jic File to EPCQ . 646.3Erase the EPCQ device . 65Chapter 7 PCIe Reference Design for Windows. 677.1PCIe System Infrastructure . 677.2PC PCIe Software SDK. 687.3PCIe Software Stack . 687.4PCIe Library API . 737.5PCIe Reference Design - Fundamental . 787.6PCIe Reference Design – DDR3 . 84Chapter 8 PCIe Reference Design for Linux . 908.1PCIe System Infrastructure . 908.2PC PCIe Software SDK. 918.3PCIe Software Stack . 918.4PCIe Library API . 948.5PCIe Reference Design - Fundamental . 948.6PCIe Reference Design - DDR3 . 100Chapter 9Appendix . 1069.1Revision History . 1069.2Copyright Statement . 1063OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

Chapter 1OpenVINO Starter KitThe OpenVINO Starter Kit presents a robust hardware design platform built around theIntel Cyclone V FPGA, it also provides a powerful platform of reconfigurable power withhigh performance and low power processing system. The OpenVINO Starter Kit isequipped with PCIe Gen1x4, high-speed DDR3 memory, GPIO, Arduino and much morethat promises many exciting applications.The OpenVINO Starter Kit is equipped with PCIe Gen1X4 interface, it is low developmentcost, and can support users who develop mainstream applications and OpenCLapplications based on PCIe, as well as a wide range of high-speed connectivityapplications.The OpenVINO Starter Kit contains all the tools needed to use the board in conjunctionwith a computer that runs the Microsoft Windows 7 or later.1.1 Package ContentsFigure 1-1 OpenVINO Starter Kit package contents4OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

OpenVINO Starter Kit package includes1.OpenVINO Starter Kit2.OpenVINO Starter Kit Quick Start Guide3.PCIe Bracket (Installed)4.Fan (Installed)5.Screw and Silicon Footstands Package6.AC Power Cord7.Power Adapter8.USB to mini-USB Cable1.2 OpenVINO Starter Kit System CDThe OpenVINO Starter Kit System CD contains all the documents and supportingmaterials associated with OpenVINO Starter Kit, including the user manual, system builder,reference designs, and device datasheets. Users can download this system CD from thelink http://OpenVINO Starter Kit.terasic.com/.1.3 Getting HelpHere are the addresses where you can get help if you encounter any problems: Terasic Inc. 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan Email:[email protected] Tel.: 886-3-575-0880 Website:http://OpenVINO Starter Kit.terasic.com/5OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

Chapter 2Introduction of the OpenVINOStarter KitThis chapter provides an introduction to the features and design characteristics of theOpenVINO Starter Kit.2.1 Layout and ComponentsFigure 2‑1 and Figure 2-2 shows a photograph of the board. It depicts the layout of theboard and indicates the location of the connectors and key components.Figure 2-1 OpenVINO Starter Kit (top view)Figure 2-2 OpenVINO Starter Kit (bottom view)6OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

The OpenVINO Starter Kit board has many features that allow users to implement a widerange of designed circuits, from simple circuits to various multimedia projects: Intel FPGA Cyclone V GX 5CGXFC9D6F27C7N device Serial configuration device– EPCQ256 USB-Blaster II onboard for programming; JTAG Mode UART to USB (USB Mini-B connector) PCIe Gen1x4 1GB DDR3 SDRAM (32-bit data bus) 64MB SDRAM (16-bit data bus) 4 push-buttons 4 slide switches 4 green LED Two 7-segment displays Four 50MHz clock sources from the clock generator One Arduino header Two 40 pin GPIO header2.2 Block Diagram of the OpenVINO Starter KitFigure 2-3 is the block diagram of the board. All the connections are established throughthe Cyclone V FPGA device to provide maximum flexibility for users. Users can configurethe FPGA to implement any system design.Figure 2-3 Block diagram of OpenVINO Starter Kit board7OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

Detailed information about Figure 2-3 are listed below. FPGA Device Cyclone V 5CGXFC9D6F27C7N device 301K programmable logic elements 13,917 Kbit/s embedded memory 8 fractional PLLs 2 hard memory controllers Nine 3.125G Transceivers Configuration and Debug Quad Serial Configuration device – EPCQ256 Onboard USB-Blaster II (Mini-B USB connector) Memory Device 64MB (32Mx16) SDRAM 1GB (2x256Mx16) DDR3 SDRAM Communication UART to USB(USB Mini-B connector) PCIe Gen1x4 Connectors Two 40 Pin GPIO header,features of each GPIO connector 36 General GPIO Pins Support to configureas 8 LVDS TX and LVDS RX With diode protection Configurable I/O standards (voltage levels: 3.3/2.5/1.8/1.5V)One Arduino Uno Revision 3 header Analog ADC Interface: SPI Fast through put rate:500Ksps Channel number: 8 Resolution: 12-bit Analog input range:0 4.096 VDigital IO With diode protection8OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

SMA IN/OUT 3.3V Single-end input and output Switches/ Buttons/ Indicators 5 user Keys (4 general keys, 1 CPU RESET n) 4 user switches 4 LED Two 7-segment displays Power 12V DC Input PCIe 12V Input Cooling System 12V Fan with 5000 Rotational Speed9OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

Chapter 3Using the OpenVINO Starter KitThis chapter provides how to instructions to use the board and describes the peripherals.3.1 Configuring the Cyclone V FPGAThere are two types of programming method supported by OpenVINO Starter Kit:1.JTAG programming:It is named after the IEEE standards Joint Test Action Group.The configuration bitstream is downloaded directly into the Cyclone V FPGA. TheFPGA will retain its current status as long as power is applied to the board; theconfiguration information will be lost when the power is off.2.AS programming:The other programming method is Active Serial configuration. Theconfiguration bitstream is downloaded into the Intel FPGA EPCQ256 device, whichprovides non-volatile storage for the bit stream. The information is retained withinEPCQ256 even if the OpenVINO Starter Kit board is turned off. When the board ispowered on, the configuration data in the EPCQ256 device is automatically loadedinto the Cyclone V FPGA. JTAG Chain on OpenVINO Starter Kit BoardThe FPGA device can be configured through JTAG interface on the OpenVINO Starter Kitboard, but the JTAG chain must form a closed loop, which allows a Quartus II programmerto the detect FPGA device.Figure 3‑1 illustrates the JTAG chain on OpenVINO Starter Kit board.Figure 3‑1 Path of the JTAG chain10OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

Configure the FPGA in JTAG ModeThere is one FPGA device on the JTAG chain. The following shows how the FPGA isprogrammed in JTAG mode step by step.1.Open the Quartus II programmer under Quartus Prime Tools and click “Auto Detect”,as circled in Figure 3‑2.Figure 3‑2 Detect FPGA device in JTAG mode2.Select detected device associated with the board, as circled in Figure 3‑3.Figure 3‑3 Select 5CGXFC9D611OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

3.The FPGA is detected, as shown in Figure 3‑4.Figure 3‑4 FPGA detected in Quartus programmer4.Right click on the FPGA device and select Change File to open the .sof file to beprogrammed, as highlighted in Figure 3‑5.Figure 3‑5 Open the .sof file to be programmed into the FPGA device5.Select the .sof file to be programmed, as shown in Figure 3‑6.12OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

Figure 3‑6 Select the .sof file to be programmed into the FPGA device6. Click “Program/Configure” check box and then click “Start” button to download the .soffile into the FPGA device, as shown in Figure 3‑7.Figure 3‑7 Program .sof file into the FPGA device Configure the FPGA in AS Mode The OpenVINO Starter Kit board uses the EPCQ256 device to storeconfiguration data for the Cyclone V FPGA. This configuration data is13OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

automatically loaded from the quad serial configuration device chip into theFPGA when the board is powered up Users need to use Serial Flash Loader (SFL) to program the EPCQ256 devicevia JTAG interface. The FPGA-based SFL is a soft intellectual property (IP) core within the FPGAthat bridges the JTAG and Flash interfaces. The SFL Megafunction is availablein Quartus Prime.Figure 3 ‑ 8 shows the programming method whenadopting SFL solution. Please refer to Chapter 6 Program the EPCQ for the basic programminginstructions on the serial configuration device.Figure 3‑8 Programming a quad serial configuration device with SFL solution3.2 Board Status ElementsIn addition to the 4 LEDs that the FPGA device can control, there are 4 indicators whichcan indicate the board status, as shown in Figure 3‑9, please refer the details in Table 3‑1.14OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

Figure 3‑9 LED Indicators on OpenVINO Starter KitTable 3‑1 LED IndicatorsLED NameSignal NameDescriptionD312V PowerIlluminates when 12V power is activeD43JTAG RXIlluminates when USB Blaster II receives dataD44JTAG TXIlluminates when USB Blaster II transmits dataD42CONF DONEIlluminates when FPGA is configured successfully3.3 Clock CircuitryFigure 3-10 shows the default frequency of all external clocks to the Cyclone V FPGA.The 50MHz is generated by a crystal oscillator. The 50MHz clock signals connected to theFPGA are used as clock sources for user logic. The board also includes two SMAconnectors which can be used to connect an external clock source to the board or to drivea clock signal in/out through the SMA connector. All these clock inputs are connected tothe phase locked loops (PLL) clock input pins of the FPGA to allow users to use theseclocks as a source clock for the PLL circuit.The associated pin assignment for clock inputs to FPGA I/O pins is listed in Table 3‑2.Figure 3-10 Block diagram of the clock distribution on OpenVINO Starter KitTable 3‑2 Pin Assignment of Clock InputsSignal NameFPGA PinNo.DirectionCLOCK 50 B3B PIN T13 InputCLOCK 50 B4A PIN U12 InputCLOCK 50 B5B PIN R20 InputDescriptionI/O Standard50MHz clock input (Bank 3B) 1.5 V50MHz clock input (Bank 4A) 1.5 V50MHz clock input (Bank 5B) 3.3-V LVTTL15OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

CLOCK 50 B6A PIN N20CLOCK 50 B7A PIN H12CLOCK 50 B8A PIN N9SMA CLKINPIN T21SMA CLKOUT PIN Y25InputInputInputInputOutput50MHz clock input (Bank 6A)50MHz clock input (Bank 7A)50MHz clock input (Bank 8A)Externa(SMA) clock inputExterna (SMA) clock output3.3-V LVTTL3.3-V LVTTL3.3-V LVTTL3.3-V LVTTL3.3-V LVTTL3.4 Peripherals Connected to the FPGAThis section describes the interfaces connected to the FPGA. Users can control or monitordifferent interfaces with user logic from the FPGA.3.4.1 User Push-buttons, Switches and LEDsThe board has four push-buttons connected to the FPGA, as shown in Figure 3-11.Schmitt trigger circuit is implemented and acts as a switch debounce in Figure 3-12 forthe push-buttons connector. The four push-buttons are named KEY0, KEY1, KEY2, andKEY3; they are coming out of the Schmitt trigger device and are connected directly to theCyclone V FPGA. The push-button generates a high logic level when it is not pressed andprovides a low logic level when pressed. Since the push-buttons are debounced, they canbe used as reset inputs in a circuit.Figure 3-11 Connections between the push-buttons and the Cyclone V FPGAPushbutton depressedPushbutton releasedBeforeDebouncingSchmitt TriggerDebounced16OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

Figure 3-12 Switch debouncingThere are four slide switches connected to the FPGA, as shown in Figure 3-13. Theseswitches are not debounced and are to be used as level-sensitive data inputs to a circuit.Each switch is connected directly and individually to the FPGA. When the switch is set tothe DOWN position (towards the edge of the board), it generates a low logic level to theFPGA. When the switch is set to the UP position, a high logic level is generated to theFPGA.Figure 3-13 Connections between the slide switches and Cyclone V FPGAThere are also four user-controllable LEDs connected to the FPGA. Each LED is drivendirectly and individually by the Cyclone V FPGA; driving its associated pin to a high logiclevel or low level to turn the LED on or off, respectively. Figure 3-14 shows the connectionsbetween LEDs and Cyclone V FPGA. Table 3‑3、Table 3‑4 and Table 3‑5 list the pinassignment of user push-buttons, switches, and LEDs.17OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

Figure 3-14 Connections between the LEDs and the Cyclone V FPGATable 3‑3 Pin Assignment of Slide SwitchesSwitch Name FPGA Pin No.DirectionDescriptionI/O StandardSW[0]PIN G20InputSlide Switch [0]3.3-V LVTTLSW[1]PIN F21InputSlide Switch [1]3.3-V LVTTLSW[2]PIN E21InputSlide Switch [2]3.3-V LVTTLSW[3]PIN H19InputSlide Switch [3]3.3-V LVTTLTable 3‑4 Pin Assignment of Push-buttonsKey NameFPGA Pin No. DirectionCPU RESET n PIN AB24InputDescriptionPIN M21InputKEY[1]PIN K25InputKEY[2]PIN K26InputKEY[3]PIN G26InputStandardGenerate a high logic level when 3.3-Vit is not pressedKEY[0]I/OLVTTL3.3-VLVTTLGenerate a high logic level when 3.3-Vit is not pressed. Four push-LVTTLbuttons (KEY0, KEY1, KEY2 and 3.3-VKEY3) are debounced.LVTTL3.3-VLVTTL18OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

Table 3‑5 LED Pin Assignment of LEDsLEDNameLED[0]FPGA Pin No.DirectionPIN U20OutputI/ODescriptionStandard3.3-VLVTTLLED[1]PIN T19OutputDrive high logic 1 to I/O pin to 3.3-VLVTTLturn the LED on.LED[2]PIN Y24OutputDrive lowh logic 0 to I/O pin to 3.3-Vturn the LED off.LED[3]PIN Y23LVTTLOutput3.3-VLVTTL3.4.2 7-Segment DisplaysOpenVINO Starter Kit has two 7-segment displays. Figure 3-15 shows the connection ofseven segments (common anode) to pins on Cyclone V FPGA。The segment can beturned on or off by applying a low logic level or high logic level from the FPGA, respectively.Each segment in a display is indexed from 0 to 6, with corresponding positions given inFigure 3-15. Table 3‑6 shows the pin assignment of FPGA to the 7-segment displays.Figure 3-15 Connections between the 7-segment displays and Cyclone V FPGATable 3‑6 Pin Assignment of 7-segment DisplaysHEX NameFPGAPinNo.HEX0 DPPIN AA6HEX0[0]PIN T8HEX0[1]PIN P26I/ODirectionDescriptionOutputSeven Segment Digit 0 DPOutputOutputStandardSeven Segment Digit 0[0]Seven Segment Digit 0[1]3.3-VLVTTL3.3-VLVTTL3.3-V19OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

LVTTLHEX0[2]PIN V8HEX0[3]PIN U7HEX0[4]PIN U25HEX0[5]PIN W8HEX0[6]PIN U26HEX1 DPPIN V25HEX1[0]PIN T7HEX1[1]PIN W20HEX1[2]PIN AB6HEX1[3]PIN AC22HEX1[4]PIN Y9HEX1[5]PIN W21HEX1[6]PIN tOutputOutputOutputOutputOutputSeven Segment Digit 0[2]Seven Segment Digit 0[3]Seven Segment Digit 0[4]Seven Segment Digit 0[5]Seven Segment Digit 0[6]Seven Segment Digit 1 DPSeven Segment Digit 1[0]Seven Segment Digit 1[1]Seven Segment Digit 1[2]Seven Segment Digit 1[3]Seven Segment Digit 1[4]Seven Segment Digit 1[5]Seven Segment Digit VTTL3.3-VLVTTL3.3-VLVTTL3.3-VLVTTL3.4.3 SDRAM MemoryThe OpenVINO Starter Kit features 64MB of SDRAM with a single 64MB (32Mx16)SDRAM chip. The chipconsists of 16-bit data line, control line, and address line connected to the FPGA. Thischip uses the 3.3V LVCMOS signaling standard. Connections between the FPGA andSDRAM are shown in Figure 3‑16, and the pin assignment is listed in Table 3‑7.20OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

Figure 3‑16 Connections between the FPGA and SDRAMTable 3‑7 Pin Assignment of SDRAMSignal NameFPGA Pin No. Direction DescriptionI/O StandardDRAM CLKPIN F26OutputSDRAM Clock3.3-V LVTTLDRAM CKEPIN E25OutputSDRAM Clock Enable3.3-V LVTTLDRAM ADDR[0] PIN D26OutputSDRAM Address[0]3.3-V LVTTLDRAM ADDR[1] PIN H20OutputSDRAM Address[1]3.3-V LVTTLDRAM ADDR[2] PIN F23OutputSDRAM Address[2]3.3-V LVTTLDRAM ADDR[3] PIN G22OutputSDRAM Address[3]3.3-V LVTTLDRAM ADDR[4] PIN B25OutputSDRAM Address[4]3.3-V LVTTLDRAM ADDR[5] PIN D22OutputSDRAM Address[5]3.3-V LVTTLDRAM ADDR[6] PIN C25OutputSDRAM Address[6]3.3-V LVTTLDRAM ADDR[7] PIN E23OutputSDRAM Address[7]3.3-V LVTTLDRAM ADDR[8] PIN B26OutputSDRAM Address[8]3.3-V LVTTLDRAM ADDR[9] PIN E24OutputSDRAM Address[9]3.3-V LVTTLDRAM ADDR[10] PIN D25OutputSDRAM Address[10]3.3-V LVTTLDRAM ADDR[11] PIN M26OutputSDRAM Address[11]3.3-V LVTTLDRAM ADDR[12] PIN M25OutputSDRAM Address[12]3.3-V LVTTLDRAM BA[0]PIN J20OutputSDRAM Bank Address[0]3.3-V LVTTLDRAM BA[1]PIN H22OutputSDRAM Bank Address[1]3.3-V LVTTLDRAM DQ[0]PIN L24InoutSDRAM Data[0]3.3-V LVTTLDRAM DQ[1]PIN M24InoutSDRAM Data[1]3.3-V LVTTLDRAM DQ[2]PIN N23InoutSDRAM Data[2]3.3-V LVTTLDRAM DQ[3]PIN K23InoutSDRAM Data[3]3.3-V LVTTL21OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

DRAM DQ[4]PIN H24InoutSDRAM Data[4]3.3-V LVTTLDRAM DQ[5]PIN J23InoutSDRAM Data[5]3.3-V LVTTLDRAM DQ[6]PIN K24InoutSDRAM Data[6]3.3-V LVTTLDRAM DQ[7]PIN L22InoutSDRAM Data[7]3.3-V LVTTLDRAM DQ[8]PIN G25InoutSDRAM Data[8]3.3-V LVTTLDRAM DQ[9]PIN G24InoutSDRAM Data[9]3.3-V LVTTLDRAM DQ[10]PIN H25InoutSDRAM Data[10]3.3-V LVTTLDRAM DQ[11]PIN J21InoutSDRAM Data[11]3.3-V LVTTLDRAM DQ[12]PIN L23InoutSDRAM Data[12]3.3-V LVTTLDRAM DQ[13]PIN K21InoutSDRAM Data[13]3.3-V LVTTLDRAM DQ[14]PIN N24InoutSDRAM Data[14]3.3-V LVTTLDRAM DQ[15]PIN M22InoutSDRAM Data[15]3.3-V LVTTLDRAM LDQMPIN H23OutputDQ[7:0] SDRAM Data Mask3.3-V LVTTLDRAM UDQMPIN F24OutputDQ[15:8] SDRAM Data Mask 3.3-V LVTTLDRAM CS nPIN F22OutputSDRAM Chip Select3.3-V LVTTLDRAM WE nPIN J25OutputSDRAM Write Enable3.3-V LVTTLDRAM CAS nPIN J26OutputSDRAMDRAM RAS nPIN E26ColumnAddressStrobeOutput3.3-V LVTTLSDRAM Row Address Strobe 3.3-V LVTTL3.4.4 DDR3 MemoryOpenVINO Starter Kit supports 1GB of DDR3 SDRAM comprising of two x16 bit DDR3devices. The signals are connected to the dedicated Hard Memory Controller for FPGAI/O banks and the target speed is 400MHz. Figure 3‑17 shows the connections betweenthe DDR3 and Cyclone V FPGA. Table 3‑8 lists the pin assignment of the DDR3 and itsdescription with I/O standard.Figure 3‑17 Connections between FPGA and DDR322OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

Table 3‑8 Pin Assignment of DDR3 MemorySignal NameFPGAPin DirectionDescriptionI/O StandardNo.DDR3 ADDR[0]PIN AE6OutputDDR3 Address[0]SSTL-15 Class IDDR3 ADDR[1]PIN AF6OutputDDR3 Address[1]SSTL-15 Class IDDR3 ADDR[2]PIN AF7OutputDDR3 Address[2]SSTL-15 Class IDDR3 ADDR[3]PIN AF8OutputDDR3 Address[3]SSTL-15 Class IDDR3 ADDR[4]PIN U10OutputDDR3 Address[4]SSTL-15 Class IDDR3 ADDR[5]PIN U11OutputDDR3 Address[5]SSTL-15 Class IDDR3 ADDR[6]PIN AE9OutputDDR3 Address[6]SSTL-15 Class IDDR3 ADDR[7]PIN AF9OutputDDR3 Address[7]SSTL-15 Class IDDR3 ADDR[8]PIN AB12OutputDDR3 Address[8]SSTL-15 Class IDDR3 ADDR[9]PIN AB11OutputDDR3 Address[9]SSTL-15 Class IDDR3 ADDR[10]PIN AC9OutputDDR3 Address[10]SSTL-15 Class IDDR3 ADDR[11]PIN AC8OutputDDR3 Address[11]SSTL-15 Class IDDR3 ADDR[12]PIN AB10OutputDDR3 Address[12]SSTL-15 Class IDDR3 ADDR[13]PIN AC10OutputDDR3 Address[13]SSTL-15 Class IDDR3 ADDR[14]PIN W11OutputDDR3 Address[14]SSTL-15 Class IDDR3 BA[0]PIN V10OutputDDR3 Bank Address[0]SSTL-15 Class IDDR3 BA[1]PIN AD8OutputDDR3 Bank Address[1]SSTL-15 Class IDDR3 BA[2]PIN AE8OutputDDR3 Bank Address[2]SSTL-15 Class IDDR3 CK pPIN N10DDR3 CK nPIN P10DDR3 CKEPIN AF14DDR3 DQS p[0]PIN V13DDR3 DQS p[1]PIN U14DDR3 DQS p[2]PIN V15DDR3 DQS p[3]PIN W16DDR3 DQS n[0]PIN W13OutputOutputOutputInoutInoutInoutInoutInoutDDR3 Clock pDDR3 Clock nDDR3 Clock EnableDDR3 Data Strobe p[0]DDR3 Data Strobe p[1]DDR3 Data Strobe p[2]DDR3 Data Strobe p[3]DDR3 Data Strobe n[0]Differential1.5-VSSTL Class IDifferential1.5-VSSTL Class ISSTL-15 Class IDifferential1.5-VSSTL Class IDifferential1.5-VSSTL Class IDifferential1.5-VSSTL Class IDifferential1.5-VSSTL Class IDifferential1.5-VSSTL Class I23OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

InoutPIN V14DDR3 DQS n[2]PIN W15DDR3 DQS n[3]PIN W17DDR3 DQ[0]PIN AA14InoutDDR3 Data[0]SSTL-15 Class IDDR3 DQ[1]PIN Y14InoutDDR3 Data[1]SSTL-15 Class IDDR3 DQ[2]PIN AD11InoutDDR3 Data[2]SSTL-15 Class IDDR3 DQ[3]PIN AD12InoutDDR3 Data[3]SSTL-15 Class IDDR3 DQ[4]PIN Y13InoutDDR3 Data[4]SSTL-15 Class IDDR3 DQ[5]PIN W12InoutDDR3 Data[5]SSTL-15 Class IDDR3 DQ[6]PIN AD10InoutDDR3 Data[6]SSTL-15 Class IDDR3 DQ[7]PIN AF12InoutDDR3 Data[7]SSTL-15 Class IDDR3 DQ[8]PIN AC15InoutDDR3 Data[8]SSTL-15 Class IDDR3 DQ[9]PIN AB15InoutDDR3 Data[9]SSTL-15 Class IDDR3 DQ[10]PIN AC14InoutDDR3 Data[10]SSTL-15 Class IDDR3 DQ[11]PIN AF13InoutDDR3 Data[11]SSTL-15 Class IDDR3 DQ[12]PIN AB16InoutDDR3 Data[12]SSTL-15 Class IDDR3 DQ[13]PIN AA16InoutDDR3 Data[13]SSTL-15 Class IDDR3 DQ[14]PIN AE14InoutDDR3 Data[14]SSTL-15 Class IDDR3 DQ[15]PIN AF18InoutDDR3 Data[15]SSTL-15 Class IDDR3 DQ[16]PIN AD16InoutDDR3 Data[16]SSTL-15 Class IDDR3 DQ[17]PIN AD17InoutDDR3 Data[17]SSTL-15 Class IDDR3 DQ[18]PIN AC18InoutDDR3 Data[18]SSTL-15 Class IDDR3 DQ[19]PIN AF19InoutDDR3 Data[19]SSTL-15 Class IDDR3 DQ[20]PIN AC17InoutDDR3 Data[20]SSTL-15 Class IDDR3 DQ[21]PIN AB17InoutDDR3 Data[21]SSTL-15 Class IDDR3 DQ[22]PIN AF21InoutDDR3 Data[22]SSTL-15 Class IDDR3 DQ[23]PIN AE21InoutDDR3 Data[23]SSTL-15 Class IDDR3 DQ[24]PIN AE15InoutDDR3 Data[24]SSTL-15 Class IDDR3 DQ[25]PIN AE16InoutDDR3 Data[25]SSTL-15 Class IDDR3 DQ[26]PIN AC20InoutDDR3 Data[26]SSTL-15 Class IDDR3 DQ[27]PIN AD21InoutDDR3 Data[27]SSTL-15 Class IDDR3 DQ[28]PIN AF16InoutDDR3 Data[28]SSTL-15 Class IDDR3 DQ[29]PIN AF17InoutDDR3 Data[29]SSTL-15 Class IDDR3 DQ[30]PIN AD23InoutDDR3 Data[30]SSTL-15 Class IInoutInoutDDR3 Data Strobe n[1]DifferentialDDR3 DQS n[1]DDR3 Data Strobe n[2]DDR3 Data Strobe n[3]1.5-VSSTL Class IDifferential1.5-VSSTL Class IDifferential1.5-VSSTL Class I24OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

DDR3 DQ[31]PIN AF23InoutDDR3 Data[31]SSTL-15 Class IDDR3 DM[0]PIN AF11OutputDDR3 Data Mask[0]SSTL-15 Class IDDR3 DM[1]PIN AE18OutputDDR3 Data Mask[1]SSTL-15 Class IDDR3 DM[2]PIN AE20OutputDDR3 Data Mask[2]SSTL-15 Class IDDR3 DM[3]PIN AE24OutputDDR3 Data Mask[3]SSTL-15 Class IDDR3 CS nPIN R11OutputDDR3 Chip SelectSSTL-15 Class IDDR3 WE nPIN T9OutputDDR3 Write EnableSSTL-15 Class IDDR3 CAS nPIN W10OutputDDR3 Column AddressDDR3 RAS nPIN Y10DDR3 RESET nPIN AE19OutputDDR3 ResetDDR3 ODTPIN AD13OutputDDR3 On-die Termination SSTL-15 Class IDDR3 RZQPIN AE11InputStrobeOutputDDR3RowAddressStrobeExternal reference ball foroutput drive calibrationSSTL-15 Class ISSTL-15 Class ISSTL-15 Class I1.5 V3.4.5 UART to USBThe OpenVINO Starter Kit has one UART interface. The physical interface is implementedby UART-USB onboard bridge from a CP2102N chip to the host with a USB Mini-Bconnector. More information about the chip is available on the manufacturer’s website, orin the directory \Datasheets\UART TO USB of OpenVINO Starter Kit system CD. Figure3‑18 shows the connections between the FPGA, CP2102N chip, and the USB Mini-Bconnector. Table 3‑9 lists the pin assignment of UART interface connected to the FPGA.Figure 3‑18 Connections between the FPGA, CP2102N chip and USB Mini-Bconnector25OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

Table 3‑9 Pin Assignment of UART InterfaceSignal NameFPGA Pin No. Direction DescriptionI/O StandardUART TXUART RXUART CTSUART RTSPIN P21PIN P22PIN W25PIN W263.3-V LVTTL3.3-V LVTTL3.3-V LVTTL3.3-V LVTTLOutputInputInputOutputUART TransmitterUART ReceiverUART Clear to SendUART Request to Send3.4.6 Arduino Uno R3 Expansion HeaderThe OpenVINO Starter Kit provides provides Arduino Uno revision 3 compatibilityexpansion header which comes with four independent headers. The expansion headerhas 17 user pins (16pins GPIO and 1pin Reset) connected directly to Cyclone V GX FPGA.8-Pin Analog input connects to the ADC, and also provides DC 5V (VCC5), DC 3.3V(VCC3P3 and IOREF), and three GND pins. Please refer to Figure 3-19 for detailed pinout information. The blue font represents the Arduino Uno R3 board pin-out definition.Figure 3-19 All the pin-out signal name of the Arduino Uno connector26OpenVINO Starter Kit User ManualMarch 15, 2019www.terasic.com.cn

The 16 GPIO pins are provided to the Arduino Header for digital I/O. Among these 16GPIO pins, two pins possess both analog and digital functionalities according to theArduino Header settings. The MCU on the Arduino main board can select either the analogor digital function. Unfortunately, this selection can't be done with the FPGA and userswould have to use the corresponding jumpers to make the selection.Table 3-10 lists allthe pin assignments of the Arduino Uno connector (digital), signal names relative toCyclone V GX FPGA.Table 3-10 Pin Assignments for Arduino Uno Expansion Header connectorSignal NameFPGA Pin No.DirectionDescriptionI/O StandardADC SCKPIN R26OutputSerial Data Clock3.3-V LVTTLADC SDOPIN AB26InputADC SDIPIN AA26OutputADC CONVSTPIN T26OuputARD IO[0]PIN Y26InoutArduino IO03.3-V LVTTLARD IO[1]PIN V23InoutArduino IO13.3-V LVTTLARD IO[2]PIN V24InoutArduino IO23.3-V LVTTLARD IO[3]PIN U24InoutArduino IO33.3-V LVTTLARD IO[4]PIN T24InoutArduino IO43.3-V LVTTLARD IO[5]PIN T23InoutArduino IO53.3-V LVTTLARD IO[6]PIN T22InoutArduino IO63.3-V LVTTLARD IO[7]PIN R24InoutArduino IO73.3-V LVTTLARD IO[8]PIN P20InoutArduino IO83.3-V LVTTLARD IO[9]PIN R23InoutArduino IO93.3-V LVTTLARD IO[10]PIN R25InoutArduino IO103.3-V LVTTLARD IO[11]PIN P23InoutArduino IO113.3-V LVTTLARD IO[12]PIN AC25InoutArduino IO123.3-V LVTTLARD IO[13]PIN AD25InoutArduino IO133.3-V LVTTLARD IO[14]PIN AB25InoutArduino IO143.3-V LVTTLARD IO[15]PIN AA24InoutArduino IO153.3-V LVTTLSerial Data Out (ADC toFPGA)Serial Data Input(FPGA to ADC)Conversion Start3.3-V LVTTL3.3-V LVTTL3.3-V LVTTLBesides 16 pins for digital GPIO, there are also 8 analog inputs on the Arduino Uno R3Expansion Header. Consequently, we use ADC LTC2308 from Linear Technology on theboard for possible future analog-to-digital applica

OpenVINO Starter Kit User Manual March 15, 2019 www.terasic.com.cn 1 . OpenVINO Starter Kit User Manual March 15, 2019 . One Arduino header Two 40 pin GPIO header 2.2 Block Diagram of the OpenVINO Starter Kit Figure 2-3 is the block diagram of the board. All the connections are established through